完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chen, SL | en_US |
dc.contributor.author | Ker, MD | en_US |
dc.date.accessioned | 2014-12-08T15:18:48Z | - |
dc.date.available | 2014-12-08T15:18:48Z | - |
dc.date.issued | 2005-07-01 | en_US |
dc.identifier.issn | 1057-7130 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/TCSII.2005.850409 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/13511 | - |
dc.description.abstract | A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-mu m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | gate-oxide reliability | en_US |
dc.subject | input-output (I/O) | en_US |
dc.subject | mixed-voltage interface | en_US |
dc.subject | Schmitt trigger | en_US |
dc.title | A new Schmitt trigger circuit in a 0.13-mu m 1/2.5-V CMOS process to receive 3.3-V input signals | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/TCSII.2005.850409 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | en_US |
dc.citation.volume | 52 | en_US |
dc.citation.issue | 7 | en_US |
dc.citation.spage | 361 | en_US |
dc.citation.epage | 365 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000230551500001 | - |
dc.citation.woscount | 17 | - |
顯示於類別: | 期刊論文 |