完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | He, ChiaHua | en_US |
dc.contributor.author | Lee, Ming-Daou | en_US |
dc.contributor.author | Pan, Chen-Ling | en_US |
dc.contributor.author | Lai, Erb-Kun | en_US |
dc.contributor.author | Yao, Yeong-Der | en_US |
dc.contributor.author | Hsieh, Kuang-Yeu | en_US |
dc.contributor.author | Liu, Rich | en_US |
dc.contributor.author | Lu, Chih-Yuan | en_US |
dc.date.accessioned | 2017-04-21T06:49:08Z | - |
dc.date.available | 2017-04-21T06:49:08Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.isbn | 978-1-4244-0584-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135149 | - |
dc.description.abstract | We report the first demonstration of a multilevel cell (MLC) resistance device using a self-aligned WO, film prepared by plasma oxidation. The 2-bit/cell operation is achieved by applying a series of 1.5V programming pulses. The device shows high thermal stability and good data retention. The resistance change can be attributed to variable-range hopping and Ohmic transport mechanisms. This device has the potential for future low-voltage, 3-dimentioanl nonvolatile memory with multiple bits per layer. In addition, no additional mask is needed to form the self-aligned device. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A 2-bit/cell, maskless, self-aligned resistance memory with high thermal stability | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS | en_US |
dc.citation.spage | 98 | en_US |
dc.citation.epage | + | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000247059300045 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |