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dc.contributor.authorHe, ChiaHuaen_US
dc.contributor.authorLee, Ming-Daouen_US
dc.contributor.authorPan, Chen-Lingen_US
dc.contributor.authorLai, Erb-Kunen_US
dc.contributor.authorYao, Yeong-Deren_US
dc.contributor.authorHsieh, Kuang-Yeuen_US
dc.contributor.authorLiu, Richen_US
dc.contributor.authorLu, Chih-Yuanen_US
dc.date.accessioned2017-04-21T06:49:08Z-
dc.date.available2017-04-21T06:49:08Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0584-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/135149-
dc.description.abstractWe report the first demonstration of a multilevel cell (MLC) resistance device using a self-aligned WO, film prepared by plasma oxidation. The 2-bit/cell operation is achieved by applying a series of 1.5V programming pulses. The device shows high thermal stability and good data retention. The resistance change can be attributed to variable-range hopping and Ohmic transport mechanisms. This device has the potential for future low-voltage, 3-dimentioanl nonvolatile memory with multiple bits per layer. In addition, no additional mask is needed to form the self-aligned device.en_US
dc.language.isoen_USen_US
dc.titleA 2-bit/cell, maskless, self-aligned resistance memory with high thermal stabilityen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage98en_US
dc.citation.epage+en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000247059300045en_US
dc.citation.woscount0en_US
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