標題: | On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design |
作者: | Lu, Chao-Hung Chen, Hung-Ming Liu, Chien-Nan Jimmy 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2007 |
摘要: | With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-drop and simultaneous switching noise, and decoupling capacitance (decap) insertion is commonly applied to alleviate the noise. There exist some approaches to addressing this issue, but they suffer either from over-design problem or late decap insertion during design stage. In this paper, we propose a methodology to insert decap in a more efficient and effective way during early design stage in area-array designs. The experimental results are encouraging. Compared with other approaches in [15] and [12], we have inserted enough decap to meet supply noise constraint while others employ more area. |
URI: | http://hdl.handle.net/11536/135174 |
ISBN: | 978-1-4244-0629-6 |
ISSN: | 2153-6961 |
期刊: | PROCEEDINGS OF THE ASP-DAC 2007 |
起始頁: | 792 |
結束頁: | + |
顯示於類別: | 會議論文 |