在混合性IC設計中實現最小化基底噪音與符合類比電路對稱性Floorplan

Abstract

近幾年來，在高階混合性信號(mixed-signal)電路中為了能克服基底雜訊(substrate noise)與製程變異問題，通常於類比電路部份需要以對稱的方式放置，而於高雜訊數位電路需要遠離類比電路以防雜訊干擾。在佈局(floorplan)的時候，對於類比電路中的對稱區塊，我們提出一個簡單且有效的方法，把屬於同一群類比區塊放置在一起且能滿足對稱限制下達到最緊密的區塊佈局，並使用基底噪音模型(substrate noise model)處理高雜訊數位區塊對於類比電路的干擾。我們使用順序對(sequence-pair)以及最長子順序對(longest common subsequence)演算法來實現。為了得到有效的解答，我們分別對類比區塊與數位區塊進行二階段式(two-phase)佈局方法，在第一階段模擬冶煉(simulated annealing)中交互執行配置類比區塊的對稱群與非對稱群，在第二階段中處理數位區塊雜訊最小化對類比區塊之干擾的佈區。最後，我們和近年來的論文所提出的實驗數據比較，從數據我們證實可以得到有效的結果。

In recent years, in order to handle substrate noise and process variation in high-end mixed-signal circuit, analog circuits are often required placement symmetrically to the axis, and high noise digital circuits need to far aware form noise interference to analog blocks. In floorplan process, for the symmetry components of the analog circuits, we propose a simple and efficient method to obtain the closest blocks placement of the analog cells of the some symmetry groups satisfying the symmetry constraints, and handle the digital blocks of high noise interference to analog blocks by using substrate noise model. We apply sequence-pair and LCS (Longest Common Subsequence) algorithm to implement the floorplan. In order to obtain solutions effectively, the analog blocks and digital blocks are implemented by two-phase method separately. In first phase, to execute the simulated annealing with the positions of the symmetry groups and non-symmetry blocks, and in second phase to achieve a floorplan with minimize digital blocks noise interference to analog blocks. Then we compare our experiment results to the papers with symmetry constraints and mixed-signal SOC (System-On Chip) floorplan with minimize substrate noise recently, and demonstrate the effectiveness of our approach by experiment result.