標題: | Simultaneous power supply planning and noise avoidance in floorplan design |
作者: | Chen, HM Huang, LD Liu, IM Wong, MDF 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | floorplanning;physical design;power supply planning;signal integrity |
公開日期: | 1-四月-2005 |
摘要: | With today's advanced integrated circuit manufacturing technology in deep submicron (DSM) environment, we can integrate entire electronic systems on a single system on a chip. However, without careful power supply planning in layout, the design of chips will suffer from local hot spots, insufficient power supply, and signal integrity problems. Postfloorplanning or postroute methodologies in solving power delivery and signal integrity problems have been applied but they will cause a long turnaround time, which adds costly delays to time-to-market. In this paper, we study the problem of simultaneous power supply planning and noise avoidance as early as in the floorplanning stage. We show that the problem of simultaneous power supply planning and noise avoidance can be formulated as a constrained maximum flow problem and present an efficient yet effective heuristic to handle the problem. Experimental results are encouraging. With a slight increase of total wirelength, we achieve almost no static IR (voltage)-drop requirement violation in meeting the current and power demand requirement imposed by the circuit blocks compared with a traditional floorplanner and 45.7% of improvement on a Delta I noise constraint violation compared wit the approach that only considers power supply planning. |
URI: | http://dx.doi.org/10.1109/TCAD.2005.844088 http://hdl.handle.net/11536/13865 |
ISSN: | 0278-0070 |
DOI: | 10.1109/TCAD.2005.844088 |
期刊: | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
Volume: | 24 |
Issue: | 4 |
起始頁: | 578 |
結束頁: | 587 |
顯示於類別: | 期刊論文 |