標題: On Minimizing Various Sources of Noise and Meeting Symmetry Constraint in Mixed-Signal SoC Floorplan Design
作者: Lin, Chung-Hsin
Chen, Hung-Ming
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2009
摘要: In recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC f oorplan with the two-phase approach. In the first phase, we place the symmetry groups and non-symmetry blocks by sequence pair representation with improved implementation. In the second phase, we obtain a I oorplan with minimized digital blocks noise interference to analog blocks by the effective decap fills with substrate noise model. We have compared our experimental results with the recent works in symmetry constraints and mixed-signal SOC f oorplan with minimized substrate noise. The results demonstrate the effectiveness of our approach.
URI: http://dx.doi.org/10.1109/ASQED.2009.5206291
http://hdl.handle.net/11536/135606
ISBN: 978-1-4244-4951-4
DOI: 10.1109/ASQED.2009.5206291
期刊: 2009 1ST ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN
起始頁: 96
結束頁: +
顯示於類別:會議論文