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dc.contributor.authorLin, Chung-Hsinen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.date.accessioned2017-04-21T06:48:39Z-
dc.date.available2017-04-21T06:48:39Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-4951-4en_US
dc.identifier.urihttp://dx.doi.org/10.1109/ASQED.2009.5206291en_US
dc.identifier.urihttp://hdl.handle.net/11536/135606-
dc.description.abstractIn recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC f oorplan with the two-phase approach. In the first phase, we place the symmetry groups and non-symmetry blocks by sequence pair representation with improved implementation. In the second phase, we obtain a I oorplan with minimized digital blocks noise interference to analog blocks by the effective decap fills with substrate noise model. We have compared our experimental results with the recent works in symmetry constraints and mixed-signal SOC f oorplan with minimized substrate noise. The results demonstrate the effectiveness of our approach.en_US
dc.language.isoen_USen_US
dc.titleOn Minimizing Various Sources of Noise and Meeting Symmetry Constraint in Mixed-Signal SoC Floorplan Designen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1109/ASQED.2009.5206291en_US
dc.identifier.journal2009 1ST ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGNen_US
dc.citation.spage96en_US
dc.citation.epage+en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000273597000019en_US
dc.citation.woscount0en_US
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