標題: Programming efficiency of stacked-gate flash memories with high-kappa dielectrics
作者: Chen, Y. Y.
Chien, C. H.
Kin, K. T.
Lou, J. C.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2006
摘要: The programming efficiency of high-permittivity (K) inter-poly dielectrics (IPDs) and tunnel dielectrics (TDs) on the stacked-gate flash memory performance is evaluated. By 2D MEDICI simulation, stacked-gate flash memories with high-K IPDs clearly exhibited significant improvement in operation speed over those with conventional oxide/nitride/oxide IPD programmed with either channel Fowler-Nordheim (CFN) or channel hot electron (CHE) injection. Choosing HfO2 as the IPD and using CFN programming scheme, the operating voltage can be reduced by more than 48% under a typical lops programming time. However, the effect of high-kappa TDs was quite different when compared with high-K IPDs. High-kappa TDs were only beneficial for memories programmed with CHE injection instead of CFN tunneling. The operating voltage can be reduced by more than 27% under lops programming time by choosing HfO2 as both the IPD and TD with CHE programming scheme. Due to the contrary improvement in programming schemes, high-kappa IPDs and TDs were suitable for next-generation NAND-and NOR-type stacked-gate flash memories, respectively.
URI: http://dx.doi.org/10.1109/NANOEL.2006.1609734
http://hdl.handle.net/11536/135192
ISBN: 978-0-7803-9357-8
DOI: 10.1109/NANOEL.2006.1609734
期刊: 2006 IEEE CONFERENCE ON EMERGING TECHNOLOGIES - NANOELECTRONICS
起始頁: 302
結束頁: +
顯示於類別:會議論文