Improved Device Characteristics in Charge-Trapping-Engineered Flash Memory Using High-kappa Dielectrics

Abstract

The much shallower trap energy in Si3N4 of [poly-Si]-SiO2-Si3N4-SiO2- Si (SONOS) charge-trapping flash (CTF) device than conventional poly-Si floating gate flash is the fundamental challenge for CTF device. We have pioneered the high-trapping layer CTF memory to increase the trapping energy, where the AlGaN has a large conduction band offset to barrier oxide layer close to conventional poly-Si floating gate. Further device performance improvement is achieved using the novel Charge-Trapping-Engineered Flash (CTEF) device with double barriers for carrier confinements and double shallow-/deep-trapping layers for charge storage. Excellent memory device integrities of large extrapolated 10-year retention of 3.8 V at 150 degrees C, 4 logic levels MLC operation, very fast 100 mu s write speed and good 100,000 cycling stress are measured at the same time. These excellent results may allow further down-scaling the flash memory for additional nodes.