標題: Improved Device Characteristics in Charge-Trapping-Engineered Flash Memory Using High-kappa Dielectrics
作者: Chin, Albert
Lin, S. H.
Tsai, C. Y.
Yeh, F. S.
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2009
摘要: The much shallower trap energy in Si3N4 of [poly-Si]-SiO2-Si3N4-SiO2- Si (SONOS) charge-trapping flash (CTF) device than conventional poly-Si floating gate flash is the fundamental challenge for CTF device. We have pioneered the high-trapping layer CTF memory to increase the trapping energy, where the AlGaN has a large conduction band offset to barrier oxide layer close to conventional poly-Si floating gate. Further device performance improvement is achieved using the novel Charge-Trapping-Engineered Flash (CTEF) device with double barriers for carrier confinements and double shallow-/deep-trapping layers for charge storage. Excellent memory device integrities of large extrapolated 10-year retention of 3.8 V at 150 degrees C, 4 logic levels MLC operation, very fast 100 mu s write speed and good 100,000 cycling stress are measured at the same time. These excellent results may allow further down-scaling the flash memory for additional nodes.
URI: http://hdl.handle.net/11536/24789
http://dx.doi.org/10.1149/1.3206644
ISBN: 978-1-60768-093-2; 978-1-56677-743-8
ISSN: 1938-5862
DOI: 10.1149/1.3206644
期刊: PHYSICS AND TECHNOLOGY OF HIGH-K GATE DIELECTRICS 7
Volume: 25
Issue: 6
起始頁: 447
結束頁: 455
顯示於類別:會議論文