Low Power Green Electronic Devices

Abstract

The IC chips consume a large amount of energy globally and will continue to increase in the near future. The present IC is a charge-based technology that has logic and memory functions to mimic the human brain. To operate the IC at higher speed, the CMOS inverter of logic IC needs to deliver higher current to charge the capacitors. Thus higher inversion charge (Q(inv)) is required in CMOS devices. The conventional method to increase Qinv in MOSFET is to scale down the gate oxide thickness (t(ox)) that also improves the short channel effect. Unfortunately, the scaling tox has reached an ultra-thin thickness of 1.2 nm at 65 nm node CMOS, which causes high gate leakage and DC power (PDC) consumption by direct quantum-mechanical tunneling. Alternatively, higher Qinv can also be obtained by using high dielectric constant (kappa) from fundamental physics of Q=CV. We pioneered the high-kappa gate dielectric CMOS starting 1998. Nevertheless, the unwanted high transistor threshold voltage (V-t) is the major challenge. Using unique dipole charge of La2O3 and Al2O3 high-kappa dielectrics, low V-t n- and p-MOSFETs were achieved at 0.6 0.9 nm equivalent-oxide thickness (EOT). Such La2O3 and Al2O3 high-kappa dielectrics have been successfully implemented in 32-nm gate-first CMOS manufacture. To further lower the AC power (P-AC) of CV2/2, we invented the small E-G defect-free Ge-on-Insulator (GOI or GeOI) MOSFET. The 2.5X higher hole mobility and 1.6X better electron mobility were reached in Ge CMOS at 1 1.4 nm EOT that enable the high-performance Ge logic at lower V-d and P-AC. The P-AC can be further lowered down by our initiated 3-dimensional (3D) IC based on the Ge CMOS. Low P-AC non-volatile memory is also required for IC function. Applying high-kappa dielectrics into flash memory, fast 100 mu s speed and low write voltage of 10 V were achieved and listed in the Intl. Technology Roadmap for Semiconductors (ITRS). Such high-kappa layers can improve the controllability of charge-storage layer and realize simpler planar structure. At present, the high-kappa flash memory has been successfully implemented at 20 nm 128 Gb array manufacture. These high-kappa CMOS and flash memory realize the low power green electronic devices.