標題: Improving the retention and endurance characteristics of charge-trapping memory by using double quantum barriers
作者: Lin, S. H.
Yang, H. J.
Chen, W. B.
Yeh, F. S.
McAlister, Sean P.
Chin, Albert
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: erase;high-kappa;nonvolatile memory;program
公開日期: 1-七月-2008
摘要: We have studied the performance of double-quantum-barrier [TaN - Ir(3)Si] - [HfAlO - LaAlO(3)] - Hf(0.3)N(0.2)O(0.5) - [HfAlO - SiO(2)]-Si charge-trapping memory devices. These devices display good characteristics in terms of their +/- 9-V program/erase (P/E) voltage, 100-mu s P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 degrees C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced-interface trap generation.
URI: http://dx.doi.org/10.1109/TED.2008.924435
http://hdl.handle.net/11536/8610
ISSN: 0018-9383
DOI: 10.1109/TED.2008.924435
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 55
Issue: 7
起始頁: 1708
結束頁: 1713
顯示於類別:期刊論文


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