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dc.contributor.authorLin, S. H.en_US
dc.contributor.authorYang, H. J.en_US
dc.contributor.authorChen, W. B.en_US
dc.contributor.authorYeh, F. S.en_US
dc.contributor.authorMcAlister, Sean P.en_US
dc.contributor.authorChin, Alberten_US
dc.date.accessioned2014-12-08T15:11:13Z-
dc.date.available2014-12-08T15:11:13Z-
dc.date.issued2008-07-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2008.924435en_US
dc.identifier.urihttp://hdl.handle.net/11536/8610-
dc.description.abstractWe have studied the performance of double-quantum-barrier [TaN - Ir(3)Si] - [HfAlO - LaAlO(3)] - Hf(0.3)N(0.2)O(0.5) - [HfAlO - SiO(2)]-Si charge-trapping memory devices. These devices display good characteristics in terms of their +/- 9-V program/erase (P/E) voltage, 100-mu s P/E speed, initial 3.2-V memory window, and ten-year extrapolated data retention window of 2.4 V at 150 degrees C. The retention decay rate is significantly better than single-barrier MONOS devices, as is the cycled retention data, due to the reduced-interface trap generation.en_US
dc.language.isoen_USen_US
dc.subjecteraseen_US
dc.subjecthigh-kappaen_US
dc.subjectnonvolatile memoryen_US
dc.subjectprogramen_US
dc.titleImproving the retention and endurance characteristics of charge-trapping memory by using double quantum barriersen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2008.924435en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume55en_US
dc.citation.issue7en_US
dc.citation.spage1708en_US
dc.citation.epage1713en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000257330100016-
dc.citation.woscount8-
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