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dc.contributor.authorYen, Shiang-Shiouen_US
dc.contributor.authorCheng, Chun-Huen_US
dc.contributor.authorLan, Yu-Pinen_US
dc.contributor.authorChiu, Yu-Chienen_US
dc.contributor.authorFan, Chia-Chien_US
dc.contributor.authorHsu, Hsiao-Hsuanen_US
dc.contributor.authorChang, Shao-Chinen_US
dc.contributor.authorJiang, Zhe-Weien_US
dc.contributor.authorHung, Li-Yueen_US
dc.contributor.authorTsai, Chi-Chungen_US
dc.contributor.authorChang, Chun-Yenen_US
dc.date.accessioned2017-04-21T06:48:58Z-
dc.date.available2017-04-21T06:48:58Z-
dc.date.issued2016-04en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.7567/JJAP.55.04ER10en_US
dc.identifier.urihttp://hdl.handle.net/11536/135212-
dc.description.abstractHigh electrostatic discharge (ESD) protection robustness and good transient-induced latchup immunity are two important issues for high voltage integrate circuit application. In this study, we report a high-voltage-n-type-field (HVNF) implantation to act as the body ties blocking layer in segmented topology silicon-controlled-rectifier (SCR) structure in 0.11 mu m 32 V high voltage process. This body ties blocking layer eliminate the elevated triggered voltage in segmented technique. Using a large resistance as shunt resistor in resistor assisted triggered SCRs stacking structure, the double snapback phenomenon is eliminate. The series SCR could be decoupled a sufficient voltage drop to turned-on when a very low current flow through the shunt resistor. The holding voltage and the failure current of 22 V and 3.4 A are achieved in the best condition of segmented topology SCR stacking structure, respectively. It improves the latchup immunity at high voltage ICs application. On the other hand, the triggered voltage almost keep the same value which is identical to SCR single cell without using segmented topology. (C) 2016 The Japan Society of Applied Physicsen_US
dc.language.isoen_USen_US
dc.titleHigh holding voltage segmentation stacking silicon-controlled-rectifier structure with field implant as body ties blocking layeren_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.7567/JJAP.55.04ER10en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICSen_US
dc.citation.volume55en_US
dc.citation.issue4en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department友訊交大聯合研發中心zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentD Link NCTU Joint Res Ctren_US
dc.identifier.wosnumberWOS:000373929400166en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper