高壓BCD製程之靜電放電防護元件設計與實現

Abstract

在smart power technology中，高壓 (high-voltage, HV) 電晶體已經廣泛運用在顯示器積體電路 (integrated circuits, ICs) 、電源供應 (power supplies) 、電源管理 (power management) ，和汽車電子 (automotive electronics) 應用上。為了克服在高壓電晶體中的高工作電壓，製程上的複雜度與確保高壓元件可靠度的困難度也隨之增加。因此，在如此惡劣工作環境下所引發的栓鎖 (latch-up) 現象對於在靜電放電 (electrostatic discharge, ESD) 可靠度的考量上更具有挑戰性。 有效率的靜電放電防護設計對於要求可靠度的高壓電晶體而言是極重要的。為了確保靜電放電防護元件的效率和可靠性，其靜電放電防護元件的電壓-電流 (I-V) 特性曲線圖必須落在靜電放電防護設計窗口 (ESD protection design window) 的範圍內。也就是說靜電放電防護元件的觸發電壓 (trigger voltage, Vt1) 必須比內部電路的崩潰電壓 (VBD, internal) 還要低，且靜電放電保護元件的持有電壓 (Vhold) 必須大於工作電壓 (VDD) 。 在高壓製程中，雙載子接面電晶體 (bipolar junction transistors, BJTs) 、高壓金氧半場效電晶體 (HV MOSFET) 和矽控整流器 (silicon controlled rectifier, SCR) 已經普遍被當作靜電放電防護元件。在這些元件中以矽控整流器最為吸引人。因為矽控整流器在最小的面積下有最高的二次崩潰電流 (It2) 和最小的導通電阻 (Ron) 。然而，在正常電路工作下，因為雙載子注入效應 (double-carrier injection) 和寄生的正回授機制 (regenerative feedback mechanism) 所造成矽控整流器的低持有電壓特性將會導致被當做電源間靜電放電箝制電路 (power-rail ESD clamp circuit) 使用的矽控整流器更容易發生栓鎖現象。因此，增加靜電放電防護元件的持有電壓和降低栓鎖現象的發生是高壓靜電放電防護設計中重要的課題。 在高壓製程中，許多針對增加靜電放電防護元件的栓鎖免疫能力已經被發展。其中一種方法是增加靜電放電防護元件的持有電壓使大於工作電壓，另一個方法是增加靜電放電防護元件的觸發電流 (Itrig) 或持有電流 (Ihold) 使大於最小的栓鎖觸發電流 (ILU) 。因為栓鎖現象是一種毫秒的可靠度測試，所以在判斷栓鎖免疫能力上使用DC量測的持有電壓、觸發電流和持有電流比使用傳輸線系統 (transmission-line-pulsing, TLP) 量測的值當作依據更具有說服力。 在本篇論文中，具有高栓鎖免疫能力的靜電放電防護元件已被設計與發展並成功的在 0.5-□m 16-V bipolar CMOS DMOS (BCD) 製程中獲得驗證。在整篇論文中採用矽控整流器當做靜電放電防護元件因為其具有優秀的靜電放電防護表現。從DC 的量測結果發現，藉由 N+-Buried Layer (NBL) 的加入可以增加矽控整流器的持有電流。另外，具有高暫態栓鎖免疫能力的靜電放電防護架構可以利用堆疊元件的方式去實現。

High-voltage (HV) transistors in smart power technologies have been extensively used for display driver integrated circuits (ICs), power supplies, power management and automotive electronics. However, the process complexity and the difficulty to guarantee the reliability of HV devices are greatly increased for the sake of sustaining such high operating voltage in HV ICs. As a result, the electrostatic discharge (ESD) reliability becomes challenging due to the severe latch-up threat in such a harsh environment. The ESD protection design with high efficiency is vital to the HV ICs for the requirement of reliability. To ensure the effectiveness and reliability of an ESD protection design, it has been generally approved that the I-V characteristics of ESD protection devices should locate within the ESD protection design window which defines the trigger voltage (Vt1) of ESD protection devices to be lower than the both junction and gate-oxide breakdown voltages of internal circuits (VBD,internal) and the snapback holding voltage (Vhold) larger than the power supply voltage (VDD). In HV technology, bipolar junction transistors, HV MOSFET and silicon controlled rectifier (SCR) have been used as on-chip ESD protection devices. Among the ESD protection devices, the SCR device is attractive and applicable for ESD protection because it exhibits extremely high failure current and low dynamic on-resistance with occupying the smallest layout area. Unfortunately, the impact of extremely low holding voltage resulted from double-carrier injection and inherent regenerative feedback mechanism causes SCR to be susceptible to quasi-static latch-up or transient-induced latch-up (TLU) danger under normal circuit operating condition, especially while SCR is used in the power-rail ESD clamp circuit. Consequently, ESD design effort is usually focused on boosting the holding voltage of ESD protection devices and minimizing the latch-up risk in HV ICs. Several ESD protection structures aimed at increasing the latch-up immunity have been investigated and reported in HV ICs. One way is to increase the holding voltage of ESD protection devices to be larger than the power supply voltage, and the other way is to increase the trigger or holding current of ESD protection devices above certain minimum latch-up triggered current to prevent latch-up during normal circuit operating condition. In addition, the ESD protection devices immunity against latch-up referred to the transmission-line-pulsing (TLP)-measured holding voltage, holding current and trigger current is insufficient because the latch-up event is a reliability test with the time duration longer than millisecond. Therefore, the holding voltage, holding current and trigger current measured from a dc curve tracer is more convincing than that measured by the TLP system while judging the validity of latch-up susceptibility. In this thesis, the ESD protection devices with high latch-up immunity have been designed and developed, and successfully verified in a 0.5-□m 16-V bipolar CMOS DMOS (BCD) processes. The SCR devices are adopted as ESD protection devices in this work because of their superior ESD performance. From the dc experimental results, the high holding currents of the single SCR devices are accomplished by the implantation of N+-buried layer (NBL). Besides, the high immunity against transient-induced latch-up can be realized by the stacked configuration of SCR devices.