完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Huang, Juin-Hau | en_US |
| dc.contributor.author | Lin, Chih Hsien | en_US |
| dc.contributor.author | Jou, Shyh-Jye | en_US |
| dc.date.accessioned | 2017-04-21T06:48:25Z | - |
| dc.date.available | 2017-04-21T06:48:25Z | - |
| dc.date.issued | 2006 | en_US |
| dc.identifier.isbn | 1-4244-0179-8 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/135217 | - |
| dc.description.abstract | In this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13 mu m IP8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz. | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | Adaptive quadrature clock generator | en_US |
| dc.type | Proceedings Paper | en_US |
| dc.identifier.journal | 2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS | en_US |
| dc.citation.spage | 203 | en_US |
| dc.citation.epage | + | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.identifier.wosnumber | WOS:000239709500053 | en_US |
| dc.citation.woscount | 0 | en_US |
| 顯示於類別: | 會議論文 | |

