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dc.contributor.authorHuang, Juin-Hauen_US
dc.contributor.authorLin, Chih Hsienen_US
dc.contributor.authorJou, Shyh-Jyeen_US
dc.date.accessioned2017-04-21T06:48:25Z-
dc.date.available2017-04-21T06:48:25Z-
dc.date.issued2006en_US
dc.identifier.isbn1-4244-0179-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/135217-
dc.description.abstractIn this paper we propose the architecture for multi-phases clocking distribution. Based on QCG architecture, we propose a new adaptive QCG to increase its operation frequency range. The adaptive QCG can automatically track and lock phase difference when input frequency is different. This architecture is implemented by UMC 0.13 mu m IP8M process and employed by on-chip transceiver. The average power consumption is 6.43 mW at 2 GHz clocking frequency. The operation frequency is from 500 MHz to 2.5 GHz.en_US
dc.language.isoen_USen_US
dc.titleAdaptive quadrature clock generatoren_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage203en_US
dc.citation.epage+en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000239709500053en_US
dc.citation.woscount0en_US
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