完整後設資料紀錄
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dc.contributor.authorWang, Kuan-Chungen_US
dc.contributor.authorChen, Hung-Mingen_US
dc.date.accessioned2017-04-21T06:48:25Z-
dc.date.available2017-04-21T06:48:25Z-
dc.date.issued2006en_US
dc.identifier.isbn1-4244-0179-8en_US
dc.identifier.urihttp://hdl.handle.net/11536/135218-
dc.description.abstractIn SoC era, it is necessary to have a good and efficient large-scale modules placement for better performance estimation in chip implementation or rapid prototyping. Good representation for non-slicing floorplan/placement and ability to solve large-scale modules packing are key components. MB*-tree [10] adopted very good and well-known representation B*-tree and modern multilevel framework to handle large-scale modules floorplanning/placement. However the simulated annealing approach in declustering stage paid more time to find candidate solutions with lower cost. In this paper, we transform the epsilon-neighborhood and lambda-exchange [11] to fit in the large-scale modules placement and use it in the refinement stage of MB*-tree algorithm. The results are encouraging. We have obtained comparable or better results in area and wirelength metrics in less time spent (up to 30% improvement), compared with original MB*-tree framework.en_US
dc.language.isoen_USen_US
dc.titleMultilevel large-scale modules placement with refined neighborhood exchangeen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERSen_US
dc.citation.spage235en_US
dc.citation.epage+en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000239709500061en_US
dc.citation.woscount0en_US
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