三維積體電路的時序導向分割擺置演算法

Abstract

在現今超大型積體電路設計中，由於製程技術進步和三維技術引進，藉由直通矽晶穿孔的堆疊結構發展，來達到三維空間的垂直整合。直通矽晶穿孔取代了二維空間中過長的繞線，如何有效適當的擺置區塊和直通矽晶穿孔來改善時序問題。在此篇論文，我們將電路分層，逐一對每層執行切割擺置演算法的標準元件擺置，同時考量到擺置直通矽晶穿孔的對準條件限制，接著使用模擬退火法來減少繞線長度和優化時序，最後處理擺置的重疊問題。實驗結果顯示，三維積體電路較二維積體電路提升與改善整體效能。

The semiconductor technology has been advanced in modern VLSI design. Three-dimension (3D) concept imports an additional dimension for circuit design by using stack structures with through-silicon via (TSV). 3D ICs replace longer interconnect in 2D ICs with TSV cells. However, there are problems how to place cells and TSV cells to improve timing. In this thesis, we perform standard cell placement by min-cut partitioning for one layer after layer assignment and address alignment constraint at the same time. Then use simulated-annealing to optimize timing and reduces wirelength of interconnect. In the last, a legal placement by a greedy method removes operlap between cells and TSV cells. The experimental results show that 3D ICs improve wirelength and delay of critical path than 2D ICs.