考慮設計階層之可繞度導向平面擺置器

Abstract

擺置器在實體設計自動化中扮演一個關鍵性的角色，不僅決定了電路繞線長度的下界與電路元件的密度，也對電路的功率消耗、時序、可繞線度有著非常大的影響，以往的擺置器所考慮的條件大部分為電路的繞線長度下界與電路元件的密度。然而為了將半周長縮小，常常造成電路的元件靠得太過緊密而失去可繞線度，這樣所得到的結果並無法真的拿來使用。同時隨著製程的演進，繞線的問題變得越來越複雜，也更顯現可繞線度重要性。 因此本研究實作特定應用積體電路全域擺置器，並整合全域繞線器來提供可繞線度資訊。此全域擺置器可分為三大步驟：一、針對電路總線長下界做最小化來初始電路元件位置。二、針對線長與考慮設計階層的情形下減少電路元件重疊，來得到初步擺置完的結果。三、將初始化擺置完的結果使用全域繞線器來取得可繞線度的資訊，並利用此資訊做元件面積膨脹來取得較佳的繞線資源以增加可繞線度。

Placement plays a key role in physical design automation. Not only determining routing wire length lower bound, but also defining circuit design target density. Moreover, placement has a great impact on power consumption、timing and routability. At the same time with the technology node evolution, routing becomes more and more complex which makes routability becomes more and more important. Therefore this study implements ASIC global placer and integrates global router to get congestion information. This global placer mainly composed by three steps: I. Initial wire-length optimization. II. Design hierarchy aware initial global placement. III. Routability driven global placement including uses global router to get congestion map and using the information to do cell bloating.