考慮時鐘樹之力導向後全域擺置最佳化

Abstract

功率消耗是現今積體電路設計時其中一項主要考量的改善目標。由於時鐘樹具有高負載電容及高切換頻率的特性，因此[27]提到時鐘樹的功耗可能會占據總功耗的40%。在傳統的實體設計流程中，擺置完成之後才進行時鐘樹合成，而時鐘樹合成會建立時脈來源(clock source)到所有暫存器(register)的連線，因此時鐘樹合成所得到的結果會受限於擺置完成後暫存器的位置。 本研究實作特定應用積體電路的後全域擺置最佳化，透過結合根據分群結果來執行的三階段時鐘樹合成器到全域擺置器中，快速建立虛擬時鐘樹。此後全域擺置器根據虛擬時鐘樹的結構資訊對暫存器加入額外的時鐘樹縮減力來改善暫存器擺置的位置，擺置的結果則交由商業用軟體(SOC Encounter)來進行時鐘樹合成，改善暫存器位置的結果最後會使得時鐘樹合成完相對於未改善前能減少時鐘樹繞線長度並降低時鐘樹的切換功率。

Power consumption is one of the primary optimization objectives for modern integrated circuit designs. Clock trees can contribute more than 40% of the total power consumption due to their high frequency of switching and high capacitance [27]. In the traditional physical design flow, placement is before clock tree synthesis. Clock tree synthesis is to construct a tree to connect the clock source with all registers. Therefore optimizes clock trees are limited by the quality of register placement. This study implements ASIC post global placement optimization. We integrates a fast three stage clock tree synthesis method based on modified k-means clustering into our global placer. The fast three stage clock tree synthesis constructs the structure of the virtual clock tree. Then this post global placer add multi-level clock net contractive force according to the structure of the virtual clock tree to optimize register locations. We get the clock tree synthesis result by the commercial tool SOC Encounter. Our optimized result can not only reduce clock tree wirelength but also minimize clock net switching power.