在放置階段用多位元正反器節約時鐘功耗

Abstract

當今的積體電路中，時鐘網路功耗仍然在動態功率消耗上占很大的比例。而多位元正反器正是一種解決時鐘網路功耗的方法。多位元正反器的使用，不但可以共用正反器內的緩衝器與反向器，也可以減少時鐘網路的接點數目，節省時鐘樹上的緩衝器，也降低時鐘歪斜。前人的研究都注重在放置階段之後再將正反器合併成多位元正反器，而此時的元件位置都已經被固定下來，使得合成多位元正反器的機會變少。 本論文討論三種合併多位元正反器的方法，分別為PPMM、APIMM與FFB。其中PPMM是在放置階段後合併多位元正反器；而APIMM與FFB在放置階段同時考慮合併多位元正反器。FFB利用INTEGRA[4]取出maximal cliques並加上flip-flop bonding force，使得放置結果比單純結合放置演算法與多位元正反器合併演算法的APIMM還要好。實驗結果顯示FFB可以比PPMM多省7.3%功耗，也比APIMM省2.9%功耗。

The major part of dynamic power consumption comes from clock network in nowadays IC designs, and using multi-bit flip-flops (MBFFs) is one of the technics to reduce clock network power. Applying MBFFs not only reduces the number of built-in buffers/inverters inside the flip-flops, but also reduces the number of clock sinks. It saves a lot of buffers on the clock tree and diminishes the clock skew effect as well. The previous works focus on post-placement MBFFs merging. However, the standard cells are immovable at the post-placement stage, and thus, lowering the chances for merging MBFFs. This thesis discusses three methods for merging multi-bit flip-flops which are PPMM, APIMM, and FFB. PPMM merges MBFFs at the post-placement stage while both APIMM and FFB merge MBFFs at the placement stage. FFB extracts maximal cliques by INTEGRA[4] and applies flip-flop bonding force. It makes the placement results better than the results from APIMM, which simply combines a placement algorithm and a MBFF merging algorithm. The results show that the power saved from FFB is 7.3% more than from PPMM, and 2.9% more than from APIMM.