考慮時脈門控時序之暫存器分群演算法

Abstract

在現今的IC設計流程中，功耗 (power consumption) 是一項很大的障礙，在一個晶片中，時脈網路 (clock network) 占了功耗的很大一部分，因此今年來很多研究方向是該如何有效的降低時脈網路的功耗，時脈門控制 (clock gating) 是控制時脈網路中的暫存器 (register) 的開關，利用時脈門控元 (clock gating cell) 當暫存器在沒有運作時將它關閉達到節省工號的效果，多位元正反器 (multi-bit flip-flop) 將兩個以上的正反器合併，共用裡面的反向器 (inverter) 來節省功耗，多種電壓供應 (multiple voltage supply) 依據在晶片中不同需求，提供不同的電壓來節省工耗. 我們利用時脈門控，在考慮時序條件 (timing constraint) 的情況下，提出了一個暫存器分群 (register clustering) 的方法，使時脈門控元能最有效率的被運用，避免一個時脈門控元一次控制太多暫存器，導致附載過大，或是一次控制太少暫存器，增加不必要的時脈門控元數量。我們的實驗結果顯示，我們的方法可以將暫存器分出很平衡的群，且符合時序條件。

In modern high performance IC design, power consumption is a crucial concern. Clock network power holds a great majority of entire chip power. Some techniques have been proposed to reduce clock network power. Clock gating is an effective method that gates the clock signal of registers by introducing clock gating cells. Clock gating cells avoid the clock signal to trigger registers while there are no new data to be loaded. Multi-bit flip-flops cluster several single-bit flip-flops together and share the inverter. Multiple voltage supply provides different voltages according to different requirement on each part of the entire chip. These techniques can reduce the clock network power effectively. We consider timing constraints and propose a register clustering algorithm, avoiding a clock gating cell to drive too many registers (i.e., preventing large capacitance), or to drive too few registers (i.e., preventing a waste of clock gating cells). Our results show that we can find balanced clustering results and satisfy timing constraints.