新穎的低功耗序向元件置換演算法

Abstract

功耗已成為當代IC設計流程的主要瓶頸之一，其中時脈網路(clock network)上的功耗佔全部的三分之一甚至二分之一，所以若能有效降低時脈功耗將能有效達到省電的需求。近年來多種新型態的低功耗序向元件(Sequential element)被發表並且已被多家知名設計公司採納，包含多位元正反器(Multi-bit flip-flop)，脈波拴鎖(Pulsed-latch)等。將傳統單位元正反器置換為新型態的序向元件不只可以節省序向元件本身的功耗，更能進一步節省時脈網路的整體功耗。

在使用多位元正反器取代傳統正反器方面，我們提出在擺置後(post-placement)不影響時序(timing)之下，考慮集結多位元正反器來節省時脈功耗的方法。在使用脈波拴鎖取代傳統正反器方面，我們進一步利用時序借取的特性提高置換率。我們利用曼哈頓距離和座標轉換，將問題轉換成區間圖和線性序列，提出沿對角線集結以及螺旋式集結的方法。並且，我們的方法可以與時脈閘門(clock gating)結合。我們的成果連續兩年發表在ISPD會議，並有兩篇IEEE TCAD期刊論文，為文獻上最佳的正反器置換演算法。實驗結果顯示，將我們的演算法整合到業界的設計流程中，在擺置後執行至反器置換，可在不影響時序之下，有效降低功耗。

Clock power is the major contributor to dynamic power for modern IC design. Recently, new types of low-power sequential elements have been proposed and adopted by leading design companies. Among them, multi-bit flip-flops and pulsed-latches are two promising sequential elements. Replacing flip-flops with these low-power sequential elements can not only save the power consumption of sequential elements but also reduce clock power.

In this thesis, we propose a fast multi-bit flip-flop clustering algorithm and a novel pulsed-latch replacement approach to save power and satisfy timing constraints at post-placement. Utilizing the properties of Manhattan distance and coordinate transformation, we model the problem instance by interval graphs and use linear-sized sequences as our representation. We fully utilize the intrinsic time borrowing property of pulsed-latches and develop a spiral clustering method with clock gating consideration. Our results show that the concise representation delivers superior efficiency and effectiveness. Even under timing and placement density constraints, clock power saving still can be substantial at post-placement.