探討如何加速以半周長導線長度為導向之力導向擺置器

Abstract

擺置器在實體設計自動化中扮演一個關鍵性的角色，不僅決定了電路繞線長度的下界與電路元件的密度，也對電路的功率消耗、時序、可繞線度有著非常大的影響，而電路的繞線長度下界與電路元件的密度一向是擺置器所考慮的主要條件之一。同時隨著製程的演進，繞線的問題變得越來越複雜，而且連線的延遲也越具有影響力。 因此本研究實作特定應用積體電路擺置器，並針對半周長做最小化。此擺置器主要可分為三大步驟：一、針對電路總線長下界做最小化來初始電路元件位置。二、在考慮半周長的情形下減少電路元件的重疊，以迭代的方式來得到仍有些許違法的全域擺置的結果。三、將全域擺置完的結果給合法器使用，以得到合法擺置的結果，細部擺置再將合法化後的結果做進一步的改善之後得到最後的結果。而本研究也提出了一些方法希望能降低半周長，以及改進了一些演算法細節加速運行時間。

Placement plays a key role in physical design flow, which determines not only routing wire length lower bound but also circuit design target density. Moreover, placement has a great impact on power consumption, timing and routability. At the same time, with fast technology node evolution, routing becomes more and more complex, and wire delay becomes more critical. In this work, a global placer for ASIC designs with minimized half-perimeter wire length is realized. This global placer is mainly composed by three steps: Initial wire-length optimization, HPWL driven global placement, and legalization and detailed placement. Some methods that are used to reduce HPWL and to improve the performance of the proposed algorithm are also proposed for discussion.