ICEPL: 考慮溫度與熱梯度的熱感知平面擺置

Abstract

我們提出了兩種熱最佳化的方式並結合進初步合法化演算法的力導向廣域平面擺置，藉以減少晶片內的峰值溫度以及熱梯度。第一種方式利用熱響應的特性，定義晶片內部熱空間的基底來快速且準確地得到不同擺置結果下的溫度分布，並根據熱敏度及熱容忍度分別估量熱排斥力和熱吸引力的強弱，進而擴散位於熱點的元件。另一種則是針對功率密度高的元件，用留白的方式來相對地放大元件，除了虛擬地降低元件的功率密度外，同時也有效地保留散熱空間。在所有的實驗中，熱基底所模擬出來的溫度與GIT比較的平均誤差為0.35%。熱作用力在最大溫度及熱梯度上平均分別得到了5.16%及63.14%的改善，而繞線長度平均則是增加了10.85%。留白的結果平均增加了11.88%的繞線長度，但在最大溫度上降低了18.94%，在熱梯度則是改善了93.66%。藉由結合兩種方式，我們的實驗結果證明了額外的熱作用力可以進一步改善留白的結果。

We propose two thermal optimal techniques with rough legalization in flat force-directed global placement which abates both on-chip peak temperature and thermal gradient. In order to make use of thermal forces, bases of thermal space inside the chip are used to fast and accurately capture the temperature distribution between different placement results based on thermal response method. Then and there two innate thermal forces assessed through thermal sensitivity and thermal capability are proposed to spread cells away from hotspot. The other way is thermal padding which is an effective method to conserve white space for cells with high power density so as to reduce the power density virtually; meanwhile, the dissipation space is reserved. In all experiments, the thermal simulator via thermal bases exhibits the error of 0.35% on average compared with GIT. Thermal forces provide 5.16% and 63.14% reduction on average in peak temperature and thermal gradient respectively within 10.85% wirelength overhead and thermal paddings result in an impressive reduction in peak temperature by 18.94% and thermal gradient by 93.66% within 11.88% wirelength overhead on average. By combining the two proposed methods, our experiments demonstrate that the thermal quality resulted from thermal padding could be improved by extra thermal forces.