完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wang, Kuan-Chung | en_US |
dc.contributor.author | Chen, Hung-Ming | en_US |
dc.date.accessioned | 2017-04-21T06:48:25Z | - |
dc.date.available | 2017-04-21T06:48:25Z | - |
dc.date.issued | 2006 | en_US |
dc.identifier.isbn | 1-4244-0179-8 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135218 | - |
dc.description.abstract | In SoC era, it is necessary to have a good and efficient large-scale modules placement for better performance estimation in chip implementation or rapid prototyping. Good representation for non-slicing floorplan/placement and ability to solve large-scale modules packing are key components. MB*-tree [10] adopted very good and well-known representation B*-tree and modern multilevel framework to handle large-scale modules floorplanning/placement. However the simulated annealing approach in declustering stage paid more time to find candidate solutions with lower cost. In this paper, we transform the epsilon-neighborhood and lambda-exchange [11] to fit in the large-scale modules placement and use it in the refinement stage of MB*-tree algorithm. The results are encouraging. We have obtained comparable or better results in area and wirelength metrics in less time spent (up to 30% improvement), compared with original MB*-tree framework. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Multilevel large-scale modules placement with refined neighborhood exchange | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2006 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PAPERS | en_US |
dc.citation.spage | 235 | en_US |
dc.citation.epage | + | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000239709500061 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |