Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-mu m CMOS technology

Abstract

An ESD protection design by using the stacked P-I-N polysilicon diodes for CMOS RF integrated circuits is proposed to reduce the input capacitance and to avoid the noise coupling from the common substrate. In this paper, the dc I-V characteristics, RF S-parameters, and ESD robustness of the stacked P-I-N polysilicon diodes are investigated in a 0.18-mu m salicided CMOS process. This polysilicon diode with small parasitic capacitance and high ESD robustness is filly process compatible to general CMOS process without extra process modification.