Improvement on CDM ESD Robustness of High-Voltage Tolerant nLDMOS SCR Devices by Using Differential Doped Gate

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Chen, S. -H.	en_US
dc.contributor.author	Linten, D.	en_US
dc.contributor.author	Scholz, M.	en_US
dc.contributor.author	Hellings, G.	en_US
dc.contributor.author	Boschke, R.	en_US
dc.contributor.author	Groeseneken, G.	en_US
dc.contributor.author	Huang, Y. -C.	en_US
dc.contributor.author	Ker, M. -D.	en_US
dc.date.accessioned	2017-04-21T06:48:43Z	-
dc.date.available	2017-04-21T06:48:43Z	-
dc.date.issued	2014	en_US
dc.identifier.isbn	978-1-4799-3317-4	en_US
dc.identifier.issn	1541-7026	en_US
dc.identifier.uri	http://hdl.handle.net/11536/135272	-
dc.description.abstract	Early failure has been observed during CDM ESD stress on high-voltage tolerant nLDMOS-SCR devices in a standard low-voltage CMOS technology due to the gate oxide (GOX) degradation. In this work, we propose a special p+/n+ differential doped gate which boosts the CDM ESD failure current level with a factor of 3 to 9.	en_US
dc.language.iso	en_US	en_US
dc.subject	Electrostatic Discharge (ESD)	en_US
dc.subject	laterally diffused nMOS (nLDMOS)	en_US
dc.subject	high-voltage tolerant (HVT) devices	en_US
dc.subject	transmission line pulsing (TLP) system	en_US
dc.subject	very fast TLP system (VFTLP)	en_US
dc.subject	gate oxide reliability	en_US
dc.title	Improvement on CDM ESD Robustness of High-Voltage Tolerant nLDMOS SCR Devices by Using Differential Doped Gate	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2014 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000343833200068	en_US
dc.citation.woscount	0	en_US
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