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dc.contributor.authorLin, Hsin-Chunen_US
dc.contributor.authorLiu, Sean S. -Y.en_US
dc.contributor.authorChen, Hung-Mingen_US
dc.date.accessioned2017-04-21T06:50:13Z-
dc.date.available2017-04-21T06:50:13Z-
dc.date.issued2014en_US
dc.identifier.isbn978-1-4799-6278-5en_US
dc.identifier.issn1933-7760en_US
dc.identifier.urihttp://hdl.handle.net/11536/135327-
dc.description.abstractThe issue on reliability of the device becomes more critical as power density of device progressively increases with advancement of technology nodes. Smaller transistor and hence thinner gate oxide implies transistors are more vulnerable against an Electrostatic Discharge (ESD) event. Among the test models in ESD, Charged Device Model (CDM) has greater potential to cause catastrophic damage to the device due to its faster and larger discharging current. To protect against a CDM event, power clamps are placed across the design to offer a low resistance discharge path. However, conventional power clamp placement method to place power clamps generally relies on design experience. In this work, we propose a power clamp placement algorithm that places power clamp at strategic location which can effectively minimize number of power clamps while achieving better protection against a CDM event compared to conventional approach.en_US
dc.language.isoen_USen_US
dc.titlePlanning and Placing Power Clamps for Effective CDM Protectionen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2014 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD)en_US
dc.citation.spage663en_US
dc.citation.epage669en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000393407200102en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper