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dc.contributor.authorYeh, Chih-Tingen_US
dc.contributor.authorKer, Ming-Douen_US
dc.date.accessioned2017-04-21T06:49:46Z-
dc.date.available2017-04-21T06:49:46Z-
dc.date.issued2013en_US
dc.identifier.isbn978-1-4799-0113-5en_US
dc.identifier.isbn978-1-4799-0112-8en_US
dc.identifier.issn1541-7026en_US
dc.identifier.urihttp://hdl.handle.net/11536/135409-
dc.description.abstractA resistor-less power-rail ESD clamp circuit realized with only thin gate oxide devices, and with SCR as main ESD clamp device, has been proposed and verified in a 65nm 1V CMOS process. Skillfully utilizing the gate leakage currents to realize the equivalent resistors in the ESD-transient detection circuit, the RC-based ESD-transient detection mechanism can be achieved without using an actual resistor to reduce the layout area in I/O cells. From the measured results, the proposed power-rail ESD clamp circuit with SCR width of 45 mu m can achieve 5kV HBM and 400V MM ESD levels under the ESD stress event, while consuming only a standby leakage current of 1.43nA at 25 degrees C under the normal circuit operating condition with 1V bias.en_US
dc.language.isoen_USen_US
dc.subjectElectrostatic discharge (ESD)en_US
dc.subjectgate leakageen_US
dc.subjectpower-rail ESD clamp circuiten_US
dc.subjectsilicon-controlled rectifier (SCR)en_US
dc.titleResistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Processen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000325097500131en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper