Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process

標題:	Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process
作者:	Chiu, Po-Yen Ker, Ming-Dou Tsai, Fu-Yi Chang, Yeong-Jar 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	electrostatic discharge (ESD);ESD clamp circuit;gate leakage;silicon-controlled rectifier (SCR)
公開日期:	2009
摘要:	A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116nA at 25 degrees C, which is much smaller than that (613 mu A) of traditional design. Moreover, it can achieve ESD robustness of over 8kV in HBM and 800V in MM ESD tests, respectively.
URI:	http://hdl.handle.net/11536/17724
ISBN:	978-1-4244-2888-5
期刊:	2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2
起始頁:	750
結束頁:	753
顯示於類別：	會議論文