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dc.contributor.authorDeng, Yexinen_US
dc.contributor.authorChen, Hong-Yuen_US
dc.contributor.authorGao, Binen_US
dc.contributor.authorYu, Shimengen_US
dc.contributor.authorWu, Shih-Chiehen_US
dc.contributor.authorZhao, Liangen_US
dc.contributor.authorChen, Bingen_US
dc.contributor.authorJiang, Zizhenen_US
dc.contributor.authorLiu, Xiaoyanen_US
dc.contributor.authorHou, Tuo-Hungen_US
dc.contributor.authorNishi, Yoshioen_US
dc.contributor.authorKang, Jinfengen_US
dc.contributor.authorWong, H. -S. Philipen_US
dc.date.accessioned2017-04-21T06:49:48Z-
dc.date.available2017-04-21T06:49:48Z-
dc.date.issued2013en_US
dc.identifier.isbn978-1-4799-2306-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/135417-
dc.description.abstract3D RRAM arrays are studied at the device-and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.en_US
dc.language.isoen_USen_US
dc.titleDesign and Optimization Methodology for 3D RRAM Arraysen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000346509500156en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper