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dc.contributor.authorSu, Pen_US
dc.contributor.authorLee, Wen_US
dc.date.accessioned2014-12-08T15:18:50Z-
dc.date.available2014-12-08T15:18:50Z-
dc.date.issued2005-07-01en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TED.2005.850626en_US
dc.identifier.urihttp://hdl.handle.net/11536/13552-
dc.description.abstractThis brief demonstrates that, through the perspective of body-source built-in potential lowering (Delta V-bi), the geometry-dependent floating-body effect in state-of-the-art silicon-on-insulator (SOI) MOS-FETs can be explained and predicted by the geometry dependence of threshold voltage (V-T). The correlation between Delta V-bi and V-T unveiled in this brief is the underlying mechanism responsible for the coexistence of partially depleted and fully depleted devices in a single SOI chip.en_US
dc.language.isoen_USen_US
dc.subjectbody source built-in potential loweringen_US
dc.subjectfloating-body effecten_US
dc.subjectsilicon-on-insulator (SOI) CMOSen_US
dc.subjectthreshold voltageen_US
dc.subjectpartially depleted (PD)en_US
dc.subjectfully depleted (FID)en_US
dc.titleOn the prediction of geometry-dependent floating-body effect in SOI MOSFETsen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TED.2005.850626en_US
dc.identifier.journalIEEE TRANSACTIONS ON ELECTRON DEVICESen_US
dc.citation.volume52en_US
dc.citation.issue7en_US
dc.citation.spage1662en_US
dc.citation.epage1664en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000230123100053-
dc.citation.woscount1-
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