完整後設資料紀錄
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dc.contributor.authorPan, Tung-Mingen_US
dc.contributor.authorYen, Li-Chenen_US
dc.contributor.authorHu, Chia-Weien_US
dc.contributor.authorChao, Tien-Shengen_US
dc.date.accessioned2017-04-21T06:48:35Z-
dc.date.available2017-04-21T06:48:35Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-60768-141-0en_US
dc.identifier.issn1938-5862en_US
dc.identifier.urihttp://dx.doi.org/10.1149/1.3375607en_US
dc.identifier.urihttp://hdl.handle.net/11536/135563-
dc.description.abstractWe developed a high-k HoTiO3 gate dielectric deposited on Si (100) through reactive cosputtering. They found that the HoTiO3 dielectrics annealed at 800 degrees C exhibited excellent electrical properties such as high capacitance value, small density of interface state, almost no hysteresis voltage, and low leakage current. This phenomenon is attributed to the decrease in intrinsic defect due to the formation of well-crystallized HoTiO3 structure and composition.en_US
dc.language.isoen_USen_US
dc.titleStructural and Electrical Properties of High-k HoTiO3 Gate Dielectricsen_US
dc.typeProceedings Paperen_US
dc.identifier.doi10.1149/1.3375607en_US
dc.identifier.journalADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 6: NEW MATERIALS, PROCESSES, AND EQUIPMENTen_US
dc.citation.volume28en_US
dc.citation.issue1en_US
dc.citation.spage241en_US
dc.citation.epage245en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000313489900025en_US
dc.citation.woscount1en_US
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