完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Pan, Tung-Ming | en_US |
dc.contributor.author | Yen, Li-Chen | en_US |
dc.contributor.author | Hu, Chia-Wei | en_US |
dc.contributor.author | Chao, Tien-Sheng | en_US |
dc.date.accessioned | 2017-04-21T06:48:35Z | - |
dc.date.available | 2017-04-21T06:48:35Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-60768-141-0 | en_US |
dc.identifier.issn | 1938-5862 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1149/1.3375607 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135563 | - |
dc.description.abstract | We developed a high-k HoTiO3 gate dielectric deposited on Si (100) through reactive cosputtering. They found that the HoTiO3 dielectrics annealed at 800 degrees C exhibited excellent electrical properties such as high capacitance value, small density of interface state, almost no hysteresis voltage, and low leakage current. This phenomenon is attributed to the decrease in intrinsic defect due to the formation of well-crystallized HoTiO3 structure and composition. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Structural and Electrical Properties of High-k HoTiO3 Gate Dielectrics | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.doi | 10.1149/1.3375607 | en_US |
dc.identifier.journal | ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 6: NEW MATERIALS, PROCESSES, AND EQUIPMENT | en_US |
dc.citation.volume | 28 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.spage | 241 | en_US |
dc.citation.epage | 245 | en_US |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.identifier.wosnumber | WOS:000313489900025 | en_US |
dc.citation.woscount | 1 | en_US |
顯示於類別: | 會議論文 |