完整後設資料紀錄
DC 欄位語言
dc.contributor.authorYang, Yu-Mingen_US
dc.contributor.authorJiang, Iris Hui-Ruen_US
dc.date.accessioned2017-04-21T06:48:38Z-
dc.date.available2017-04-21T06:48:38Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-6455-5en_US
dc.identifier.issn1948-3287en_US
dc.identifier.urihttp://hdl.handle.net/11536/135595-
dc.description.abstractUnlike the mature and highly automatic flow for digital layout generation, the existing method to generate an analog layout is far from automatic because it highly depends on the designer\'s expertise. Prior endeavors are mainly dedicated to analog placement because they consider only the device symmetry constraint. This paper raises the wiring symmetry issue to analog layout: wiring symmetry is as crucial as device symmetry. Hence, we propose an analog placement and global routing algorithm to consider both types of symmetry constraints. During placement, we utilize the device folding technique to enhance the flexibility and feasibility on symmetry. Our results show that our algorithm can produce a promising initial layout to speed up the analog design process.en_US
dc.language.isoen_USen_US
dc.subjectAnalog design automationen_US
dc.subjectwiring symmetryen_US
dc.titleAnalog Placement and Global Routing Considering Wiring Symmetryen_US
dc.typeProceedings Paperen_US
dc.identifier.journalPROCEEDINGS OF THE ELEVENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2010)en_US
dc.citation.spage618en_US
dc.citation.epage623en_US
dc.contributor.department電機學院zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000393299700093en_US
dc.citation.woscount1en_US
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