A fast two-stage sample-and-hold amplifier for pipelined ADC application

doi:10.1109/DELTA.2008.58

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Ruan, Jian	en_US
dc.contributor.author	Lee, Chung Len	en_US
dc.date.accessioned	2017-04-21T06:48:53Z	-
dc.date.available	2017-04-21T06:48:53Z	-
dc.date.issued	2008	en_US
dc.identifier.isbn	978-0-7695-3110-6	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/DELTA.2008.58	en_US
dc.identifier.uri	http://hdl.handle.net/11536/135645	-
dc.description.abstract	This paper presents a differential input, two-stage structure sample-hold-amplifier (SHA) for which each stage can be designed and adjusted separately to have a large input dynamic range and fast operation speed. The clock feed through and charge injection is eliminated. The implemented SHA with a 0.18um 1.8V process shows that it can sample a 2.5 MHz signal at 40 MHz with a 63d8 SFDR and a -62 dB THD which is able to realize an ADC of 10 bit resolution.	en_US
dc.language.iso	en_US	en_US
dc.subject	sample-and-hold amplifier	en_US
dc.subject	two-stage structure	en_US
dc.subject	pipelined ADC	en_US
dc.subject	bootstrapped switch	en_US
dc.subject	bottom-plate sampling	en_US
dc.title	A fast two-stage sample-and-hold amplifier for pipelined ADC application	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.doi	10.1109/DELTA.2008.58	en_US
dc.identifier.journal	DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS	en_US
dc.citation.spage	99	en_US
dc.citation.epage	+	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000254291500020	en_US
dc.citation.woscount	0	en_US
顯示於類別：	會議論文