標題: A 802.15.3c/802.11ad Compliant 24 Gb/s FFT Processor for 60 GHz Communication Systems
作者: Davila, Henry Lopez
Liu, Chun-Yi
Liu, Wei-Chang
Huang, Shen-Jui
Jou, Shyh-Jye
Chen, Sau-Gee
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 2015
摘要: This paper, we present a 24 Gb/s 512-point 8X-parallel FFT processor for 60 GHz communication systems. The proposed design is a pipelined Multipath Delay Feedback (MDF) radix-2(3) architecture, which exploits the parallelism of the multipath scheme together with pipeline technique to achieve a high throughput rate. Besides, the proposed FFT processor is implemented with an area efficient optimized multiplier architecture that avoid the need to store the twiddle factor in memory and a dynamic scaling technique to enhance the SQNR, allowing the FFT to operate with 16-QAM and 64-QAM for single carrier (SC) and orthogonal frequency-division multiplexing(OFDM) schemes. This FFT processor has been implemented in a SC/OFDM dual-mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40nm CMOS process. The post-layout implementation results show that the proposed FFT processor is able to achieve up to 24 Gb/s throughput rate at 500MHz clock with a power consumption of 87mW and area of 0.64mm(2).
URI: http://hdl.handle.net/11536/135742
ISBN: 978-1-4673-9094-1
期刊: 2015 28TH IEEE INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE (SOCC)
起始頁: 44
結束頁: 48
Appears in Collections:Conferences Paper