完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hsiao, Frank | en_US |
dc.contributor.author | Lai, Jung-Chin | en_US |
dc.contributor.author | Hsu, Terng-Yin | en_US |
dc.date.accessioned | 2017-04-21T06:50:12Z | - |
dc.date.available | 2017-04-21T06:50:12Z | - |
dc.date.issued | 2015 | en_US |
dc.identifier.isbn | 978-1-4673-9308-9 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/135758 | - |
dc.description.abstract | This paper presents an all-digital standard cell SR-Latch based time amplifier (TA) with a variable gain of 6X and 12X. In this TA, a two-stage gain selection unit is applied to enable the TA to select either the high gain for short input pulse intervals or the low gain for long input pulse intervals. The time amplification gain is 6 in the input range of -700ps similar to 700ps, and reaches 12 if the input range is -300 similar to 300ps. We present a design that automatically detects the input pulse and switches to the proper TA gain. By applying the proposed TA, a standard cyclic TDC implemented in a UMC CMOS | en_US |
dc.language.iso | en_US | en_US |
dc.subject | TA | en_US |
dc.subject | skew calibration | en_US |
dc.subject | TDC | en_US |
dc.title | A VARIABLE-GAIN TIME AMPLIFIER WITH AUTOMATIC INTERVAL DETECTION | en_US |
dc.type | Proceedings Paper | en_US |
dc.identifier.journal | 2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | en_US |
dc.citation.spage | 263 | en_US |
dc.citation.epage | 264 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:000380449100121 | en_US |
dc.citation.woscount | 0 | en_US |
顯示於類別: | 會議論文 |