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dc.contributor.authorHsiao, Franken_US
dc.contributor.authorLai, Jung-Chinen_US
dc.contributor.authorHsu, Terng-Yinen_US
dc.date.accessioned2017-04-21T06:50:12Z-
dc.date.available2017-04-21T06:50:12Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-9308-9en_US
dc.identifier.urihttp://hdl.handle.net/11536/135758-
dc.description.abstractThis paper presents an all-digital standard cell SR-Latch based time amplifier (TA) with a variable gain of 6X and 12X. In this TA, a two-stage gain selection unit is applied to enable the TA to select either the high gain for short input pulse intervals or the low gain for long input pulse intervals. The time amplification gain is 6 in the input range of -700ps similar to 700ps, and reaches 12 if the input range is -300 similar to 300ps. We present a design that automatically detects the input pulse and switches to the proper TA gain. By applying the proposed TA, a standard cyclic TDC implemented in a UMC CMOSen_US
dc.language.isoen_USen_US
dc.subjectTAen_US
dc.subjectskew calibrationen_US
dc.subjectTDCen_US
dc.titleA VARIABLE-GAIN TIME AMPLIFIER WITH AUTOMATIC INTERVAL DETECTIONen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)en_US
dc.citation.spage263en_US
dc.citation.epage264en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000380449100121en_US
dc.citation.woscount0en_US
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