應用於類比數位轉換器之時脈抖動量測與補償技術

Abstract

在一個新式的通訊接收器中，接收到的連續類比訊號會先被一個類比數位轉換器量化成不連續的數位序列，以便在數位領域進行更複雜的訊號處理。類比數位轉換器需要一個週期性的時脈訊號做為基準以對輸入訊號進行取樣。如果取樣時脈發生抖動，類比數位轉換器會因為取樣的錯誤而造成輸出之訊號雜訊比性能下降。對於一個低速度低解析度的類比數位轉換器而言，取樣時脈抖動所造成的誤差並不是很重要。隨著通訊系統的進步，類比數位轉換器的操作速度以及解析度也隨之增加。對於一高速度高解析度的類比數位轉換器而言，準確的取樣時脈訊號是不可或缺的。 時脈訊號中之抖動可藉由一時間數位轉換器量測出來並量化成數位訊號。藉由適當的校正技術可將此數位訊號對應成時脈抖動之資訊。量測出來的抖動資訊，用在數位領域補償類比數位轉換器因取樣錯誤造成的誤差，改善輸出之訊號雜訊比。本篇論文描述一個應用於類比數位轉換器之時脈抖動量測及補償技術。 我們實現了一個65奈米互補式金氧半場效電晶體製成的7-bit、80-MS/s之時間數位轉換器。利用時間數位轉換器量測出類比數位轉換器取樣時脈之抖動。我們也提出了新的時間數位轉換器之數位校正技術。此校正技術可在背景執行，因此不會影響類比數位轉換器以及時間數位轉換器之正常工作。我們提出的技術也不會受到元件或繞線不匹配的影響，也不會對取樣時脈信號的波型敏感。我們實現之7-bit時間數位轉換器解析度為0.27ps。此時間數位轉換器佔據0.1mm^2的晶片面積，在電源供應器為1.2V下，消耗的功率為20mW。 將此時間數位轉換器應用於一16-bit類比數位轉換器之取樣時脈抖動量測與補償上，我們提出了兩種方案: 1)類比數位轉換器之取樣時脈為理想的，以及 2:)類比數位轉換器之取樣時脈訊號為主要的抖動來源。在第一種方案中，對於一個最佳化設計之鎖控延遲迴路，在類比數位轉換器之輸入為29MHz正弦波下，16-bit的類比數位轉換器可將訊號雜訊比由71.2dB改善為77.3dB。對於一個設計不良的鎖控延遲迴路則可將訊號雜訊比由60.8dB改善為74.4dB。在第二種方案中，我們提出的時脈抖動補償技術可在輸入時脈抖動之均分根值為8.2ps的情況下，達到等效於均方根值為4ps抖動之取樣效果。

In a modern communication receiver, the received continuous-time analog signal is quantized into a discrete-time digital sequence by an analog-to-digital converter (ADC) so that the complex signal processing can be performed in the digital domain. The ADC requires a periodic clock as a timing reference for input sampling. If the sampling clock exhibits jitter, the ADC su?ers from sampling errors and its signal-to-noise ratio (SNR) performance is degraded. For a low-speed low-resolution ADC, the sampling error due to clock jitter is not crucial. As the progress of advanced communication system, the operation speed and the resolution of the ADC are also increased. An accurate sampling clock is essential for a high-speed high-resolution ADC. Clock jitter can be measured and digitized by a time-to-digital converter (TDC). With appropriate calibration technique, the output code of the TDC can be translated in to the corresponding jitter information. This jitter information is then used to compensate the ADC D s sampling error in the digital domain, improving the ADC D s SNR performance. This thesis presents a clock jitter measurement and compensation scheme for analog-to-digital converters. A 7-bit 80-MS/s TDC was fabricated using a 65 nm CMOS technology. The clock jitter of an ADC is measured by the TDC. We also demonstrate a new digital calibration technique for the TDC. The calibration can be performed in the background without interrupting the normal ADC and TDC operation. The proposed technique is immune to device and interconnection mismatches, and is not sensitive to the waveforms of the input clocks either. The resolution of the 7-bit TDC is 0.27 ps. The TDC occupies a die area of 0.1mm^2 while consuming 20 mW from a 1.2 V supply. The TDC is applied to a 16-bit ADC for the clock jitter measurement and compensation. Two di?erent system scenarios are covered: 1) an ADC with a clean external clock and 2) an ADC with an external clock as the main jitter source. For the first scenario, the SNR of the 16-bit ADC is improved from 71.2 dB to 77.3 dB for an optimized delay-locked loop (DLL) and 60.8 dB to 74.4 dB for an ill-conditioned DLL by the jitter correction at a sine wave input frequency of 29 MHz. For the second scenario, the proposed jitter correction technique achieves an equivalent sampling jitter root-mean-squared value (rms) of 4 ps when the jitter rms of the original sampling clock is 8.2 ps.