標題: | ADC Clock Jitter Measurement and Correction Using a Stochastic TDC |
作者: | Fan, Chi-Wei Wu, Jieh-Tsorng 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2010 |
摘要: | The jitter of the sampling clock of an analog-to-digital converter (ADC) is measured by a stochastic time-to-digital converter (TDC). The measured jitter data are used to correct the ADC sampling error and improve its signal-to-noise ratio (SNR). The same ADC is used to calibrate the TDC in the background. Both the TDC and the ADC operate at a sampling rate of 80 MS/s. Fabricated in a 65 nm CMOS technology, the TDC consists of 127 timing comparators. The proposed jitter correction technique achieves an equivalent sampling jitter root-mean-squared value (rms) of 4 ps when the jitter rms of the original sampling clock is 8.2 ps. |
URI: | http://hdl.handle.net/11536/14609 |
ISBN: | 978-1-4244-7456-1 |
期刊: | PROCEEDINGS OF THE 2010 IEEE ASIA PACIFIC CONFERENCE ON CIRCUIT AND SYSTEM (APCCAS) |
起始頁: | 1007 |
結束頁: | 1010 |
顯示於類別: | 會議論文 |