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dc.contributor.authorArya, Pranaven_US
dc.contributor.authorHuang, Liang-Yuen_US
dc.contributor.authorLiu, Wei-Changen_US
dc.contributor.authorChang, Hsin-Tingen_US
dc.contributor.authorJen, Chih-Weien_US
dc.contributor.authorWu, Chi-Fengen_US
dc.contributor.authorJou, Shy-Jyeen_US
dc.date.accessioned2017-04-21T06:49:27Z-
dc.date.available2017-04-21T06:49:27Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4799-8745-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/135812-
dc.description.abstractThis work presents a dual mode, single carrier (SC) and high speed interface (HSI), wireless baseband receiver which implements the IEEE standards 802.15.3c 111 and 802.11.ad [2]. The proposed architecture of the baseband receive is designed as 8 parallelism with feed-forward data path reducing the operating frequency and can achieve high throughput for indoor communication. Besides, our goal is to demonstrate the system on Xilinx VC707 FPGA evaluation board and achieve multi-Gb/s data speed and low bit error rate (BER). The data rates achieved by the prototype are 1.5 Gb/s and 4.5 Gb/s for QPSK and 64QAM data in HSI mode, respectively. The specified (BER) of 10(-2) has been achieved for QPSK and 64QAM data at 8.3dB and 22.6dB, respectively.en_US
dc.language.isoen_USen_US
dc.titleGb/s Prototyping of 60GHz Indoor Wireless SC/OFDM Transmitter and Receiver on FPGA Demo Systemen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TW)en_US
dc.citation.spage204en_US
dc.citation.epage205en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380469500102en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper