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dc.contributor.authorLin, Chun-Yuen_US
dc.contributor.authorKer, Ming-Douen_US
dc.contributor.authorChang, Pin-Hsinen_US
dc.contributor.authorWang, Wen-Taien_US
dc.date.accessioned2017-04-21T06:49:46Z-
dc.date.available2017-04-21T06:49:46Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-4673-9362-1en_US
dc.identifier.urihttp://hdl.handle.net/11536/135820-
dc.description.abstractTo protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.en_US
dc.language.isoen_USen_US
dc.subjectCMOSen_US
dc.subjectelectrostatic discharge (ESD)en_US
dc.subjecthigh-k metal-gate (HKMG)en_US
dc.subjectsilicon-controlled rectifier (SCR)en_US
dc.titleStudy on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technologyen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC)en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000380447300021en_US
dc.citation.woscount0en_US
Appears in Collections:Conferences Paper