Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lin, Chun-Yu	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Chang, Pin-Hsin	en_US
dc.contributor.author	Wang, Wen-Tai	en_US
dc.date.accessioned	2017-04-21T06:49:46Z	-
dc.date.available	2017-04-21T06:49:46Z	-
dc.date.issued	2015	en_US
dc.identifier.isbn	978-1-4673-9362-1	en_US
dc.identifier.uri	http://hdl.handle.net/11536/135820	-
dc.description.abstract	To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.	en_US
dc.language.iso	en_US	en_US
dc.subject	CMOS	en_US
dc.subject	electrostatic discharge (ESD)	en_US
dc.subject	high-k metal-gate (HKMG)	en_US
dc.subject	silicon-controlled rectifier (SCR)	en_US
dc.title	Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2015 IEEE NANOTECHNOLOGY MATERIALS AND DEVICES CONFERENCE (NMDC)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000380447300021	en_US
dc.citation.woscount	0	en_US
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