標題: | Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devices |
作者: | Lai, Wei-Ting Yang, Kuo-Ching Liao, Po-Hsiang George, Thomas Li, Pei-Wen 交大名義發表 National Chiao Tung University |
公開日期: | 2015 |
摘要: | We reported a first-of-its-kind, self-aligned gate-stack heterostructure of Ge-nanoshpere-gate/SiO2/SiGechannel on Si in a single-step approach through selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on Si substrate. Good tunability on the Ge-nanoshpere size, SiO2 thickness, and SiGe-shell thickness provides a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices with size-tunable Ge gates, SiO2 gate oxide, and SiGe channels. Detailed interfacial morphologies and structural properties between the Ge nanosphere/SiO2 and SiO2/SiGe-channel were examined using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Both Al/SiO2/Genanospheres and NiGe/SiO2/SiGe MOS capacitors exhibit quite low interface trap densities of 3-5x10(11) cm(-2)eV(-1), which is beneficial for advanced Ge MOS applications. |
URI: | http://hdl.handle.net/11536/135839 |
ISBN: | 978-1-4673-7604-4 |
期刊: | 2015 SILICON NANOELECTRONICS WORKSHOP (SNW) |
顯示於類別: | 會議論文 |