ESD Protection Design with Latchup-Free Immunity in 120V SOI Process

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Huang, Yi-Jie	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Huang, Yeh-Jen	en_US
dc.contributor.author	Tsai, Chun-Chien	en_US
dc.contributor.author	Jou, Yeh-Ning	en_US
dc.contributor.author	Lin, Geeng-Lih	en_US
dc.date.accessioned	2017-04-21T06:49:12Z	-
dc.date.available	2017-04-21T06:49:12Z	-
dc.date.issued	2015	en_US
dc.identifier.isbn	978-1-5090-0259-7	en_US
dc.identifier.uri	http://hdl.handle.net/11536/135840	-
dc.description.abstract	Electrostatic discharge (ESD) protection with lowvoltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-mu m 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.	en_US
dc.language.iso	en_US	en_US
dc.title	ESD Protection Design with Latchup-Free Immunity in 120V SOI Process	en_US
dc.type	Proceedings Paper	en_US
dc.identifier.journal	2015 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S)	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000370657300004	en_US
dc.citation.woscount	0	en_US
顯示於類別：	會議論文