標題: | Compensation Circuit with Additional Junction Sensor to Enhance Latchup Immunity for CMOS Integrated Circuits |
作者: | Tsai, Hui-Wen Ker, Ming-Dou 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Latchup;electrostatic discharge (ESD) protection;guard ring |
公開日期: | 2015 |
摘要: | A circuit solution to generate compensation current that can decrease the perturbation induced by the external latchup trigger was proposed. The robustness against latchup can be improved by supporting compensation current at the pad under latch-up current test. By inserting additional junctions to sense the latchup trigger current, the injected latchup trigger current can be detected, and then the I/O or ESD-protection devices are used to generate the compensation current that decrease the perturbation to the internal circuits. The proposed design has been successfully verified in a 0.5-mu m BCD process to improve latchup immunity. |
URI: | http://hdl.handle.net/11536/135943 |
ISBN: | 978-1-4799-9877-7 |
期刊: | 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD) |
起始頁: | 256 |
結束頁: | 259 |
顯示於類別: | 會議論文 |