標題: Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current Triggers
作者: Tsai, Hui-Wen
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Latch-up;electrostatic discharge (ESD) protection;guard ring
公開日期: 1-六月-2015
摘要: The robustness against latch-up in the integrated circuits can be improved by supporting complementary current at the pad under the latch-up current test (I-test). By inserting additional junctions to form parasitic bipolar sensors, the external trigger can be monitored, and the ESD protection devices can be applied to provide such current and decrease the related perturbation to the internal circuits. The proposed design and the previous work with a single guard ring have been fabricated in the same 0.5-mu m 5-V process. The experimental results confirm the enhanced latch-up tolerance of this work and the practicability in the SOC era.
URI: http://dx.doi.org/10.1109/TDMR.2015.2424377
http://hdl.handle.net/11536/127918
ISSN: 1530-4388
DOI: 10.1109/TDMR.2015.2424377
期刊: IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
Volume: 15
起始頁: 242
結束頁: 249
顯示於類別:期刊論文