標題: | Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology |
作者: | Ker, MD Lo, WY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | design rule;guard ring;I/O cell;latchup;pickup |
公開日期: | 1-五月-2003 |
摘要: | An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances, A new latchup prevention design by adding the additional internal double guard rings between input/output cells and internal circuits is first reported in the literature, and its effectiveness has been successfully proven in three different bulk CMOS processes. I Through detailed experimental verification including temperature effect, the proposed methodology to extract compact layout rules has been established to save silicon area of CMOS ICs but still to have high enough latchup immunity. This proposed methodology has been successfully verified in a 0.5-mum nonsilicided, a 0.35-mum silicided, and a 0.25-mum silicided shallow-trench-isolation bulk CMOS processes. |
URI: | http://dx.doi.org/10.1109/TSM.2003.811885 http://hdl.handle.net/11536/27923 |
ISSN: | 0894-6507 |
DOI: | 10.1109/TSM.2003.811885 |
期刊: | IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING |
Volume: | 16 |
Issue: | 2 |
起始頁: | 319 |
結束頁: | 334 |
顯示於類別: | 期刊論文 |