標題: Comparison of Electrical Characteristics of N-type Silicon Junctionless Transistors with and without Film Profile Engineering by TCAD Simulation
作者: Tsai, Jung-Ruey
Lin, Horng-Chih
Chang, Hsiu-Fu
Shie, Bo-Shiuan
Wen, Ting-Ting
Huang, Tiao-Yuan
電子工程學系及電子研究所
奈米中心
Department of Electronics Engineering and Institute of Electronics
Nano Facility Center
公開日期: 2015
摘要: Field-effect transistors (FETs) with junctionless (JL) channels have recently attracted much attention for various applications, such as metal-oxide semiconductor thin-film transistors (TFTs) [1], memory devices [2] and Si nanowire TFTs [3, 4]. The Si junctionless (JL) transistors employing high dopant concentration (>= 10(19) cm(-3)) in the source, drain, and nano-scaled channel have been demonstrated to provide excellent electrical characteristics. More recently, film profile engineering (FPE) concept for fabricating downscaled ZnO and IGZO TFTs [5, 6] have been proposed to obtain high-on/off current ratio and great subthreshold swing. Nevertheless, it emphasizes a significant issue of source/drain (S/D) series resistance on the downscaled device performance that needs to be further verified. In this work, electrical performance of downscaled N-type Si JL TFTs with FPE channel and conventional ones will be compared with each other by Sentaurus technology computer aided design (TCAD) simulation [7].
URI: http://hdl.handle.net/11536/135841
ISBN: 978-1-4673-7604-4
期刊: 2015 SILICON NANOELECTRONICS WORKSHOP (SNW)
Appears in Collections:Conferences Paper