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dc.contributor.authorYang, Chih-Chaoen_US
dc.contributor.authorHsieh, Tung-Yingen_US
dc.contributor.authorHuang, Wen-Hsienen_US
dc.contributor.authorWu, Tsung-Taen_US
dc.contributor.authorWang, Hsing-Hsiangen_US
dc.contributor.authorShen, Chang-Hongen_US
dc.contributor.authorKao, Ming-Hsuanen_US
dc.contributor.authorYeh, Wen-Kuanen_US
dc.contributor.authorChang, Meng-Fanen_US
dc.contributor.authorWu, Meng-Chyien_US
dc.contributor.authorShieh, Jia-Minen_US
dc.date.accessioned2017-04-21T06:49:12Z-
dc.date.available2017-04-21T06:49:12Z-
dc.date.issued2015en_US
dc.identifier.isbn978-1-5090-0259-7en_US
dc.identifier.urihttp://hdl.handle.net/11536/135851-
dc.description.abstractHigh performance 3D sequentially stackable nanowire FETs and non-volatile memories (NVMs) with threshold voltage engineering and driving current boosting technologies were demonstrated by using low thermal budget nanosecond laser crystallization and laser activation technologies. The local heating laser process without damaging the underlying device/circuit realizes the across -layer and in -layer integration of high-speed 3ps logic circuits and 1-T 100ns plasma-MONOS NVMs as well as low driving-voltage 6T SRAMs with static noise margin (SNM) of 280 mV. Such logic/memory hybrid 3D sequentially integrated circuit provides power efficient computing and storage. Moreover, the monolithically stacking of Si thin-film energy harvester envisions lower power and low cost 3D(+)IC for internet of things.en_US
dc.language.isoen_USen_US
dc.subject3DICen_US
dc.subjectmonolithic 3Den_US
dc.subjectlow thermal budgeten_US
dc.subjectlaser annealen_US
dc.titleLogic/Memory Hybrid 3D Sequentially Integrated Circuit Using Low Thermal Budget Laser Processen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2015 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S)en_US
dc.contributor.department光電工程學系zh_TW
dc.contributor.departmentDepartment of Photonicsen_US
dc.identifier.wosnumberWOS:000370657300029en_US
dc.citation.woscount0en_US
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