以雷射結晶化高密度電漿成長非晶矽鍺薄膜之低溫虛擬基板

Abstract

為了滿足可攜式電子產品輕薄短小且多功能性的特色，其微處理器及記憶體需於有限空間達到高密度、高效率、低功耗等多項需求。因此，積體電路製程技術，除了持續挑戰高難度高成本的元件尺吋微縮技術外(device scaling)，以元件堆疊的概念所開發之三維積體電路技術(3D IC)，格外受到重視。根據ITRS規劃，2017年後累加型單晶片(monolithic)3D積體線路將會成為主流技術。累加型單晶片(monolithic) 3D積體線路是將元件層層疊加，且不傷害下層元件。因此，上層元件需能與後段連導線製程(Back End of the Line, BEOL)相容，其中關鍵技術之一是開發一低熱預算且高結晶性之矽通道層，此論文將詳訴本團隊利用電漿沉積系統沉積低氫含量非晶矽薄膜，並已雷射結晶技術開發高結晶性類磊晶通道層，並實現於可堆疊電晶體。 雷射結晶技術雖已開發多年，但本論文突破過去高溫的製程(600oC)，以及必須經過長時間的除氫過程(450°C 1hr)。由於高溫的製程會傷害底層元件，不利於進行3D IC的開發。本論文直接利用電漿系統所沉積低氫含量之非矽薄膜，製程溫度較低(<500℃)，且氫含量低(平均氫含量<1%)，並於雷射結晶過程不會出現氫爆、燒焦的現象。在本篇論文，我們將優化的沉積條件，開發高品質且低氫含量之電漿非晶矽薄膜，用以整合雷射結晶技術，開發高結晶矽低溫多晶矽薄膜。 本論文利用高密度電漿化學沉積系統及奈秒綠光雷射尖峰結晶技術，製作多晶矽薄膜電晶體。電漿化學沉積系統在500℃製備非晶矽薄膜，再以雷射退火技術使其轉換，藉由X光繞射儀及電子顯微鏡分析驗證多晶矽薄膜為具0.5μm晶粒之多晶矽薄膜。結合此低熱預算技術及金屬閘極結構，已成功開發出可堆疊之多晶矽薄膜電晶體。其載子遷移率可達55cm2/V-s、次臨界擺幅可低於0.3 V/Decade以及On/Off電流比可超過105。 最後，本實驗室目前正在進行非晶鍺薄膜的研究，一樣相同的方法，嘗試能沉積出可接受雷射再結晶的非晶鍺薄膜，轉換成微晶鍺薄膜。目前已有令人期待的初步結果。透過奈秒綠光雷射尖峰結晶技術，其晶粒尺寸可達1.74μm。鍺的載子移動率比矽高出二至三倍，在高速元件的開發上是重要的技術選項。

In order to meet short, light and portable electronic products versatility features, its microprocessor and memory required in a limited space to achieve high density, high efficiency, low power consumption and many other needs. Therefore, keep challenges the high cost of scaling technology is needed, but the concept of stacked components developed by three-dimensional integrated circuit technology (3D IC) is very important. According to the plan of ITRS, after 2017 accumulating single chip (monolithic) 3D-IC will become a mainstream technology. Accumulate single chip (monolithic) 3D-IC component is superimposed layers, and does not damage the underlying components. Therefore, the upper component must be able to connect with the rear section of wire process (Back End of the Line, BEOL) compatible, which is one of the key technologies to develop a low thermal budget and high crystallinity of the silicon channel layer. We use the (High-density plasma chemical vapor deposition, HDPCVD) to deposit amorphous silicon films with low hydrogen content and has laser crystallization technology to develop high class crystalline epitaxial channel layer, and to achieve in stackable transistors. Although laser crystallization technology developed over the years, but mostly in the furnace tubes with higher temperature deposited amorphous silicon thin film (600℃). Plasma deposition of silicon thin film systems at lower process temperature (<500℃), but higher hydrogen content (over 1%) will lead to hydrogen explosion in laser crystallization process. In this paper, we will optimize the deposition conditions to develop high-quality and low hydrogen content of amorphous silicon film. And develop a stackable poly-silicon thin-film by laser crystallization technology for integration. In this thesis, we use the high-density plasma chemical vapor deposition system and nanosecond green laser peak crystallization technology to produce poly-silicon thin film transistors. Plasma deposit amorphous silicon films are prepared at 500 ℃, and then converted in laser crystallized technique. X-ray diffraction and electron microscopy analysis verified that the poly-silicon film has 0.5μm grain size. This technique combined with low thermal budget has successfully developed stackable poly-silicon thin film transistor and the carrier mobility can up to 55cm2/Vs. The sub-threshold swing can be less than 0.3V/Decade, and the On/Off current ratio can exceed 105. Finally, the amorphous germanium thin film is under study. We use the same way to deposit an acceptable laser crystallized amorphous germanium film, then converted into a poly-germanium thin film. After laser crystallization, the grain size up to 1.74μm. It’s an exciting preliminary result. Because the germanium is an important element of technical options, due to the carrier mobility is higher than silicon two to three times.